Control for commutatorless motor

ABSTRACT

Three stator phase windings of a commutatorless motor are energized from a battery through power transistors. A capacitive rotor position sensor coupled to the motor rotor derives three phase square wave rotor position signals displaced 120* apart at a frequency proportional to motor speed. Three sets of logic gates receive rotor position signals as inputs and control the conduction interval of the transistors. When a motor direction switch is actuated forward, first gates of the three logic sets are opened to enable the transistors during first rotor position signals displaced 120* to generate a clockwise rotating stator field, and when the direction switch is actuated to the reverse position, second gates are opened to enable the transistors during second rotor position signals displaced 180* from the first signals to thereby shift the stator field 180* and thus reverse rotor direction. Third gates of the logic sets are opened when the motor attains a predetermined speed to enable the transistors during rotor position signals shifted 60* from the first signals to thereby vary the motor torque angle. A plurality of timing pulses are generated during each rotor position signal, variable delay means generate delay pulses from the timing pulses after a selectively adjustable time delays the delay pulses open delay gates disposed between the logic gates and the power transistors, and motor speed controlling means vary the time delay between the timing and delay pulses to thereby change the power duty cycle of the power transistors and thus control motor speed and torque.

Geiersbach et al.

CONTROL FOR COMMUTATORLESS MOTOR Inventors: Allois F. Geiersbach,Milwaukee;

Frederick A. Stich, Hales Comers,

both of Wis.

[73] Assignee: Allis-Chalmers Corporation,

Milwaukee, Wis.

[22] Filed: June 26, 1972 21 Appl. No.2 266,286

[52] U.S. Cl. 318/138, 318/227 [51] Int. Cl. ..-H02k 29/00 [58] Field ofSearch...; ..3l8/138, 171, 227, 318/230, 231

[56] References Cited UNITED STATES PATENTS 3,678.358 7/1972Kolatorowicz 318/138 3,418,550 12/1968 Kolatorowicz et a1. 318/1383,483,458 12/1969 Kirk 318/138 Primary Examiner-Gene Z. RubinsonAttrneyLee H. Kaiser et a1.

[ 7 ABSTRACT.

Three stator phase windings of a commutatorless motor are energized froma battery through power 'transistors. A capacitive rotor position sensorcoupled to the motor rotor derives three phase square wave rotorposition signals displaced apart at a frequency proportional to motorspeed. Three sets of logic gates receive rotor position signals asinputs and control the conduction interval of the transistors. When amotor direction switch is actuated forward, first gates of the threelogic sets are opened to enable the transistors during first rotorposition signals displaced 120 to generate a clockwise rotating statorfield, and when the direction switch is actuated to the reverseposition, second gates are opened to enable the transistors duringsecond rotor position signals displaced from the first signals tothereby shift the stator field 180 and thus reverse rotor direction.Third gates of the logic sets are opened when the motor attains apredetermined speed to enable the transistors during rotor positionsignals shifted 60 from the first signals to thereby vary the motortorque angle. A plurality of timing pulses are generated during eachrotor position signal, variable delay means generate delay pulses fromthe timing pulses after a selectively adjustable time delays the delaypulses open delay gates disposed between the logic gates and the powertransistors, and motor speed controlling means vary the time delaybetween the timing and delay pulses to thereby change the power dutycycle of the power transistors and thus control motor speed and torque.

52 Claims, 20 Drawing Figures P562 P567 p563? PAIENTEDJAN elm sum 1 BF 9PAIENIEUJAN BIHH SHEET 2 0F 9 PATENIEUJAN 8 NH sum 7 or 9 l CONTROL FORCOMMUTATORLESS MOTOR This invention relates to commutatorless motors andmore particularly to a control for a variable speed commutatorlessmotor.

BACKGROUND OF THE INVENTION Commutation in a conventional direct currentmotor is essentially a mechanical switching operating in which brushesand a segmented commutator cyclically reverse current through thearmature conductors in a sequence as a function of rotor position, andsuch commutation results in friction wear and sparking with attendantgeneration of radio frequency noise. in order to eliminate such defects,commutatorless D.C. motors have been developed provided with electroniccommutation means for controlling the armature current in accordancewith the rotational position of the rotor. Brushless D.C. motors arealso known which employ a permanently magnetized rotor and wherein thestator windings are energized in a cyclical sequence throughsemiconductor power switches which are sequentially gated in accordancewith the rotational position of the rotor. Variable speed synchronousmotors are also known wherein a synchro coupled to the motor rotorderives phase-displaced sine wave control signals at a frequencyproportional to motor speed which regulate a cycloconverter forenergizing the stator windings, and the phase angle and magnitude of thecontrol signals are varied as a function of motor speed to advance motortorque angle at higher motor speeds.

Prior art commutatorless motor controls which use optical or magneticrotor position sensors are, in general, unnecessarily expensive andcomplicated and have relatively low sensitivity and relatively hightemperature drift. Known commutatorless motor controls using magneticrotor position sensors have problems with D.C. offsets, while thoseemploying optical rotor position sensors have problems with dirt andvibration. Also. prior art controls for hrushless D.C. motors do nothave the desirable torque and speed characteristics of conventionaldirect current motors, while known controls for variable speedsynchronous motors either require complicated and expensive synchros forgener ating phasc-displaced sine wave control signals or necessitatccomplicated and expensive analog circuits.

OBJECTS OF THE INVENTION it is an objectof the invention to provide atorque angle control for an adjustable speed synchronous motor which issimpler and less expensive than prior art devices.

Another object of the invention is to provide an improved control for anadjustable speed synchronous motor which can be regulated over theentire speed range using only two discrete torque angles.

A further object is to provide an improved torque angle control for anadjustable speed commutatorless motor which eliminates the expensiveanalog circuits required by prior art controls and utilizes digitalcircuits to shift torque angle and to reverse motor direc tion.

Still another object of the invention is to provide an improved controlfor an adjustable speed commutaton less motor using a rotor positionsensor which generates square wave signals indicative of rotor positionand which eliminates the expensive prior art synchros which derivedphase-displaced sine wave control signals indicative of rotor position.

A still further object of the invention is to provide an improvedcontrol for a commutatorless motor wherein square wave rotor positionsignals control the conduction interval of semiconductor power switcheswhich energize the stator winding and in sequence which keeps the rotorpoles in synchronism with the rotating stator field. Another object isto provide such a control wherein the rotor position signals duringwhich the power switches are enabled can easily be changed to vary motortorque angle as a function of motor speed and/or to reverse motordirection. Still another object is to provide such a control havingnovel means to inhibit phase shift of the stator field when the motor isrotating above a predetermined speed and the motor direction switch isreversed and which, under such conditions, permits the power switches toconduct during rotor position signals which result in braking of the motor.

A still further object of the invention is to provide an improvedcontrol for a commutatorless motor wherein different rotor positionsignals control the conduction interval of the power switches and havingnovel means to control the power duty cycle of the power switches inorder to adjust motor speed and torque.

Still another object of the invention is to provide an improved controlfor commutatorless motors having electronic commutation means forcontrolling armature current in accordance with the rotational positionof the rotor and which has speed and torque characteristics comparableto those of a conventional D.C. motor while eliminating the abovedisadvantages of mechanical commutation. Another object of the inventionis to provide an improved control for a commutatorless motor which hashigh stall torque and operates over a wide speed range with smoothcontrol of speed. A still further object of the invention is to providean improved control for a commutatorless motor which permits smoothregenerative braking and smooth reversal of the direction of motorrotation. Still another object is to provide such a commutatorless motorcontrol in which efficiency is high, which is relatively low in cost andsimple to manufacture, and wherein relatively simple digital circuitscontrol sequential energization of the stator windings. A further objectof the invention is to provide such an improved control for acommutatorless motor which is particularly adapted to drive a vehicleand which, upon failure of a power switch, will not cause the vehicle tobecome uncontrollable but rather will still drive the vehicle to arepair area.

SUMMARY OF THE INVENTION A commutatorless electric motor having n phasestator windings is energized, in accordance with the invention, from apower source through controllable semiconductors (power swtiches) whichare enabled to con duct during rotor position signals displaced 360/11electrical degrees apart derived by a rotor position sen sor coupled tothe motor rotor to generate a rotating magnetic field within the stator.A logic gate set asso ciated with each phase winding comprises aplurality of logic gates which respectively receive different squarewave rotor position signals as inputs and have their outputs commonedand coupled to the associated power switch. Means responsive toactuation of a motor direction swtich to forward position opens firstgates of the n logic gate sets to enable the power swtiches during firstrotor position signals displaced 360/n electrical degrees which generatea rotating magnetic field within the stator, and is responsive toactuation of the switch in the reverse direction to open second gates toenable the power switches during second rotor position signals displaced360M degrees and also displaced 180 from the first signals to therebyshift the stator field 180 electrical degrees and thus reverse motordirection. A speed signal is derived when the rotor angular velocityexceeds a predetermined magnitude, and means responsive to the speedsignal opens third gates to enable the power switches during third rotorposition signals displaced 60 from "t'li first sr ans'ta "change themotor torque angle as a function of motor speed.

Delay gates are disposed between the logic gates and the power switches.A plurality of timing pulses are generated during each rotor positionsignal. Variable delay means generates a delay pulse from each timingpulse after a time delay. The delay pulses open the delay gates to turnon the power switches, and the variable delay means retard opening ofthe delay gates, and thus delay initiation of power switch conduction,to vary the duty cycle of the power switches and thereby control motorspeed and torque.

In the preferred embodiment each stator phase winding has a center tapwith the two windings halves joined at the center tap oppositelypolarized and each being connected in series with a power switch. Therotor position sensing means derives 11 square wave rotor positionsignals displaced 360/n degrees apart and their complements, and thepower switches associated with the oppositely polarized halves of eachstator phase winding are enabled respectively by complementary rotorposition signals so that they operate in push-pull.

DESCRIPTION OF THE DRAWINGS These and other objects and advantages ofthe invention will be more readily apparent from the following detaileddescription when considered in conjunction with the accompanyingdrawing. wherein:

FIG. 1 is a schematic diagram in block form of the commutatorless motorcontrolof a preferred embodiment of the invention; r

FIG. 2 is a schematic wiring diagram of the rotor position sensor, thesquare wave generator, and the synchronous pulse generator of thecontrol of FIG. 1;

FIGS. 3a illustrates the three-phase output square waves from the squarewave generator which indicate rotor position; FIG. 3b illustrates thetrain of 60 spaced apart timing pulses P from the synchronous pulsegenerator whose frequency is a function of motor speed; FIG. 30illustrates the train of delay pulses P after they have been delayed 30in the variable delay circuit; FIG. 3d illustrates the logic" signals 02from delay gating circuit 22 fed over lead C2 to interface circuit IFCZas a result of the delay pulses P shown in F I6. 30; and FIG. 32illustrates the current pulses CC2 conducted by power switch PSC2 as aresult of the logic signals c2 shown in FIG. 3d;

FIG. 4 is a schematic wiring diagram of the variable delay circuit;

FIG. 5 is a schematic wiring diagram of the speed switch;

FIG. 6 is a schematic wiring diagram of the speeddirection circuit, theangle-direction gating circuit, and the delay gating circuit;

FIGS. 7a, 7b, 7c and 7d show the rotor position signals which enablepower switches PSAl and PSAZ for, respectively: (a) forward motorrotation and 0 torque angle; (b) reverse rotation and 0 torque angle,(0) forward rotation and leading torque angle, and (d) reverserotationand 60 leading torque angle;

FIG. 8 is a schematic wiring diagram of the motor field currentregulator;

FIG. 9 is a schematic wiring diagram of power switch PSC2 and interfacecircuit IFC2;

FIG. 10 is a partial cross section view through a preferred embodimentof the capacitive position sensor;

FIGS. 11 and 12 are views taken along lines XI-XI and XIIXIIrespectively of FIG. 10, and

FIG. 13 shows the field current regulator characteristics. 7

DETAILED DESCRIPTION 7 Referring to the drawing, the motor of thepreferred embodiment of the invention may have the frame (not shown) ofa conventional synchronous motor with the stator winding schematicallyshown in FIG. 1 similar to that of a three-phase, wye connected,push-pull transformer. The stator has one centertapped winding perphase, and the wye configuration is made by connecting together thecenter taps of the three phase windings. Stator phase A windingcomprises a winding section AlP, termed a power winding, connected inseries with an oppositely polarized winding section, or power windingA2! and with the center tap therebetween connected to the positiveterminal of the battery and being commoned to the center tap betweenpower windings B1? and BZP of phase B stator winding and also common tothe center tap between power windings Cl? and C2P of phase C statorwinding. (In this system of notation, the first symbol designates thephase, the second symbol designates the polarity group,.and the thirdsignal designates the type of winding, power or drive). The two powerwindings (i.e., winding sections) of each phase statorwinding are ofopposite polarity, e.g., winding AlP is of opposite polarity to windingAZP, winding B1! is oppositely polarized from winding 82?. Each powerwinding AlP, AZF, BlP, BZP, ClP, and C2P is connected to a power switchwhich preferably is a silicon transistor, e. g.,.powet winding A1? iscoupled to the collector of power switch PSAI, power winding .A2P iscoupled to the collector of power switch PSA2, etc. Only one powerswitch PSC2 is shown in detail in FIG. 9.

When the two power switches of a phase, such as PSAI and PSAZ of phaseA, are operated alternately to energize the oppositely polarized powerwindings such as AlP and AZP, the direction of magnetic flux in themotor stator is reversed, even though the direction of current from thebattery through windings Al? and A2P is unchanged. Thus the powerwinding of each phase, suchas A1? and AZPofthe phase A stator winding,in conjunction with the associated power switches PSAl and PSA2 arearranged in push-pull in a manner similar to a push-pull converter.Because of the polarities of the two power windings per phase, such asAlP and A2P, each carrying unidirectional current, an alternating fluxis established in each phase of the motor stator, and the six powerswitches PSAl,

PSAI, PSBl, PSB2, PSCl and PSC2 conduct at the correct time to maintainthe desired direction rotational velocity of the stator rotatingmagnetic field.

The motor rotor R is shown schematically in FIG. 1 and may be similar toa conventional synchronous motor rotor with four non-salient field polesand a field winding FLD energized with direct current from a fieldcurrent regulator FCR described hereinafter to generate. a directcurrent magnetic field which reacts with the rotating magnetic fieldgenerated by the stator power windings A1P-C2P to produce torque on therotor R. FIG. 1 illustrates that the rotor field winding FLD isenergized through brushes, but it will be appreciated that brushes maybe eliminated if the field wind ing is energized from a unidirectionalsource including a rotating transformer (not shown) having thetransformer secondary winding and the rectifiers mounted on the motorrotor in the manner disclosed in U.S. Pat. No. 3,351,396 to La Rosehaving the same assignee as this invention or if the motor is of thesynchronous inductor type wherein magnetic poles are generated in awindingless ferromagnetic rotor by a field winding or the stator such asdisclosed in US. Pat. No. 3,584,276 to W. L. Ringland et al.

The motor stator also has a center-tapped base drive winding in eachphase with the center taps connected in wye to provide six windingsections, termed drive" windings AlD, A2D, BID, B2D, C1D, and C2D eachof which is inductively linked with the corresponding power winding ofthe same phase, e.g., drive winding AlD is inductively linked to powerwinding AIP, etc. The drive windings of each phase are of oppositepolarity, e.g., winding AID is oppositely polarized from winding A2D,and each drive winding supplies base drive power to the correspondingtransistor power switch and derives such power from the correspondingpower winding by transformer action.

POWER SWITCH The power transistor switches ISAl, PSAZ, IPSBl, PSBZ, PSCland PSC2 for power windings AlP, AZP, BlP, B2P, ClP and C2Prespectively, are shown in block form in FIG. 1 and are identical topower transistor switch PSC2 for power winding C2P shown in detail inFIG. 9 comprising a plurality of paralleled power transistors 01-08. Thenumberof paralleled transistors Ql-Q8 is determined by the requiredcurrent rating, and the series of dots in FIG. 9 indicates that anydesired number of power transistors may be utilized in the transistorpower swtich PSC2. The collectors of transistors QlQ8 are commoned andconnected to stator power winding C2P. The emitters of paralleledtransistors Q8 A8 are commoned and connected to the negative terminal Bof the battery. The bases of transistors Ql-QS are connected throughsimilar resistors (only R1, R3 and R being shown) to the negativeterminals B of the battery and are also connected through similarresistors (only R2, R4 and R16 being shown) to a base lead DR to theinterface circuit IFC2 for power switch PSC2. The base resistors Rl-Rl6insure base current Sharing by the power transistors 01-08. A diode D1connected across emitter and collector of powertransistors 01-08 inopposite polarity thereto functions as a free-wheeling diode andregenerative path during the time the motor is acting as a generator toconduct currents flowing in the direction opposite to the currentsupplied by power switch PSC2 to stator winding C2P, such as may begenerated during braking of the motor. A diode D2 coupled to a TRANSSUPP lead clamps the collectors of the power transistors 01-08 to acommon transient suppressor circuit (not shown) which is shared by allsix power switches PSAl-PSCZ.

INTERFACE CIRCUIT The interface circuits IFAl, IFA2, IFBl, IFB2, IFCland IFC2 which drive the power switches PSAl, PSA2, PSBl, PSBZ, PSCl andPSC2 respectively are shown in block form in FIG. 1 and are similar tointerface circuit IFC2 (see FIG. 9) which drives power switch PSC2. Theprincipal function of the interface circuits IFA- l-IFC2 is to step upthe power level efiiciently between the logic output from delay gatingcircuit 22 and the bases of the power switches PSAl-PSAZ, and theinterface circuits lFAl-IFCZ also protect the power switches byinterrupting the logic" signal from delay gating circuit 22 whenabnormal voltages are sensed across the power switches. The base drivelead DR from power switch PSC2 is coupled to the emitter of a base drivetransistor Q9 having its collector coupledthrough a diode 3 to drivewinding C2D (which is inductively coupled to power winding C2P). Thebase of transistor Q9 is connected through a resistor R18 to thenegative terminal -B of the battery and also to the emitter of atransistor Q10 having its collector coupled through a resistor R19 tothe positive battery terminal. The collector of transistor O9 is alsocoupled through a diode D4 and over a lead D0 to a drive oscillatorshown in block form in FIG. 1. The base of transistor Q10 is coupled toa VCL lead from a variable current limit circuit 21 shown in block formin FIG. 1 and is also coupled through a resistor R21 to the collector ofa transistor 01 l. The emitter of transistor ()1 l is connected to apositive five volt direct voltage regulator source +5V, and the base ofPNP transistor 011 is connected through a resistor R22 to a lead C2 fromdelay gating circuit 22. Interface circuit IFC2 is arranged so that alogical 0 voltage signal over lead C2 from the delay gating circuit 22will result in turning on transistors Q11, Q10 and 09 with the result ofturning power switch PSC2 on (and so that a logic 1' signal on lead C2will result in turning power switch PSC2 off).

When a power switch such as PSC2 is conducting, base current is fed backfrom the associated inductively linked power and drive windings C2P andC2D to sustain conduction of the power switch PSC2, and the magnitude ofsuch feedback base drive current is a function of the drive windingvoltage, the base-emitter voltage of the transistor power switch, andother voltage drops in the circuit. If the collector current of a powertransistor switch becomes high enough to pull the power transistorswtich out of saturation, switch the base current drive to the powertransistor switch will decrease and degenerative turn-off of the powertransistor switch will occur. In other words, the increase of collectorcurrent to the power transistor switch pulls in into the active regionand consequently increases its collector-to-emitter voltage, therebydecreasing the input to the power winding and also decreasing the outputvoltage from the corresponding drive winding and the base current driveto the power transistor. Such degenerative current limiting increasesuntil the base drive transistor Q9 for the transistor power switch turnsoff and prevents the power switch from assuming a stable operating pointin the active region where it would eventually be destroyed because ofthe generation of excessive heat.

Each phase A, B and C of the motor has two identical circuits, one foreach power switch, and the conducting periods of the two power switchesper phase (e.g., PSCl and PSC2 for phase C) are displaced 180 so that asquare wave is produced across rhe corresponding motor stator powerwindings such as ClP-CZP for full conduction. The other two phases A andB produce similar square waves with 120 displacement between phases forthe three-phase output.

Logic voltage and logic 1 voltage square wave signals over leads Al, A2,B1, B2, C1, and C2 from delay gating circuit 22 to interface circuitslFAl, IFA2, lFBl, IFB2, IFCl and IFC2 respectively control the allowablewindow during which the power switches PSAl, PSA2, PSBl, PSB2, PSCl andPSC2 may conduct. The initiation (and reinstatement) of power switchconduction is dependent upon pulses generated by drive oscillator 20.Drive oscillator 20 is triggered by a pulse over lead 78 from variabledelay circuit so that initiation of conduction by the power switchesPSA1-PSA2 will coincide with the leading edges of the logic waveformsover leads Al, A2, B1, B2, C1 and C2 from delay gating circuit 22. Driveoscillator generates a train of periodic pulses to reinstate conductionby the power switches after turn-off by current limiting.

The forward bias for power switch PSC2 is generated by drive winding C2Dand is coupled through diode D3 of interface circuit IFCZ and thecollector-emitter circuit of transistor O9 to the base of power switchPSC2, while the reverse bias for the power switch PSC2 is also generatedacross drive winding C2D and is coupled to the base of power switch PSC2through diode D6 in series with a resistance R23. The initial pulse fromdrive oscillator 20 over lead D0 is coupled through diode D4 and thecollector-emitter circuit of base drive transistor Q9 of interfacecircuit IFC2 to the base drive lead DR and the bases of powertransistors Ql-QS of power switch PSC2 to turn them on. As explainedabove, the initial pulse from drive oscillator 20 is coincident with alogic signal from delay gating circuit 22, and the negative-going logicO square wave pulse over lead C2 from delay gating circuit'22 is coupledto the base of PNP transistor 011 to turn it on. The change of voltageon the collector of transistor Ql-l turns on transistor Q10 and basedrive transistor Q9. Transistors Q11 and Q10 raise the power level ofthe square wave negativegoing logic" pulses from delay gating circuit 22and apply them to the base of base drive transistor 09. Regenerationoccurs through inductively coupled power and drive windings C2? and C2D,diode D3 and the collector-emitter circuit of base drive transistor O9to maintain power transistors 01-08 in saturation, and power switch PSC2remains cpnducting after the trigger pulse from drive oscillator 20disappears. The power switch PSC2 will remain conducting until thecoupled positive feedback can no longer support switch PSC2 insaturation. The train of periodic pulses (not shown) from driveoscillator 20 will continue for the duration of the square wave Iogic"pulses 02 (see FIG. 3d) over lead C2 from delay gating circuit 22, andif power switch PSC2 should current limit and turn off during theconduction interval, conduction will be resumed at the next pulse fromdrive oscillator 20 which 8 a is coupled through diode D4 and transistorO9 to the base of power transistors Ql-QS.

Once the logic 0 square wave c2 over lead C2 from delay gating network22 disappears and logic 1 reappears on lead C2 and the pulses from driveoscillator 20 cease, the regenerative feedback through windings C2P andC2D can no longer support the power switch PSC2 in saturation becausetransistor O9 is not conducting. The collector-to-emitter voltage oftransistors Ql-Q8 of power switch PSC2 consequently increase and therebydecrease the voltage, input to power winding C2P. Resistor R23 in serieswith diode D6 of interface circuit IFC2 provides a path for turn-offcurrent to power switch PSC2 in shunt to transistor Q9, and when powerswitch PSC2 turns off, the polarity of drive winding C2D reverses andprovides reverse bias through diode D6 and resistance R23 to the basesof the power transistors Ql-Q8 of power switch PSC2.

GENERAL THEORY OF SPEED AND DIRECTION CONTROL The two power switches ineach phase, such as power switches PSA] and PSA2 of phase A, conductapart to provide unidirectional current to the two oppositely polarizedpower windings AlP and A2P respectively of phase A to thus establish analternating flux in each phase of the motor. Capacitive position sensor1 1 determines the instantaneous motor rotor position and provides athree-phase square wave output A, A, B, B, C and C shown in' FlG..3a ata frequency proportional to motor speed and which is indicative of rotorposition and thus of the position of the rotor field with respect to thestator phase windings. The threephase position sensor output establishesthe correct stator field sequence with respect to the rotor so that thesix power switches PSAl-PSCZ conduct at the right time and in the rightsequence to maintain the desired direction and rotational velocity ofthe stator rotating field which will keep the rotor field lockedtherewith. Control of the motor is accomplished by delaying the turningon of the power switches PSALPSCZ so that they are on for less thantheir full conduction period.

If the three-phase square wave output A, A, B, B, C and C of positionsensor 11 (shown in FIG. 3a), which is synchronized to the rotorposition, were applied without delay and directly over leads A1, A2, B1,B2, C1 and C2 from delay circuit 22 to interface circuits IFAl, IFA2,lFBl, lFB2, IFCl and IFCZ respectively, the motor rotor R would rotatein the forward direction at full conduction of power switches PSAl-PSCZand with the conduction window of the power switches PSA l-PSC2 in phasewith the counter e.m.f. generated in the stator power windings by themagnetic flux of the resultant ampere turns (i.e., the resultant of therotor field winding ampere turns and the armature reaction ampereturns). Motor speed and torque are selectively controlled by varying theduty cycle of the power switches PSAl-PSCZ, i.e., the portion of theconduction window during which the power switches conduct. As the dutycycle of the power switches is increased, the average current carried bythe power windings is increased and consequently motor torque and rotorspeed are likewise increased.

1316 rotor position sensor output square waves A, A, B, B, C and C shownin FIG. 3a are inputs to the angledirection circuit 19 and determine theallowable window during which the power swit'ches PSA1-PSA2 may conduct.The point of the beginning of conduction within the conduction window bythe power switches PSAl-PSA2 is determined by the setting of a powercontrol potentiometer PCP which is an input over lead 74 to variabledelay circuit 15. Synchronous pulse generator l4 derives a train oftiming pulses P shown in FIG. 3b at a frequency proportional to motorspeed, and variable delay circuit 15 delays the pulses through a phaseangle proportional to the setting of power control potentiometer PCP toderive delay pulses P shown in FIG. 3c which initiate conduction bypower switch PSC2. The train of drive pulses over lead D are coupledthrough diode D4 and transistor Q9 of interface circuit IFC2 to thebases'of power transistors QIQ8 of power switch PSC2.

Each delay pulse P (shown in FIG. 30) from variable delay circuit (andthus the train of drive pulses from drive oscillator is continuous untilthe next synchronizing .pulse P from pulse generator 14 is applied tovariable delay circuit 15. Thus the power control potentiometer PCP setsthe delay which can vary the conduction of the power switches PSAl-PSCZfrom full-on to full-off.

The synchronous pulse generator 14 produces a timing pulse P (shown inFIG. 3b) at every square wave edge of the three-phase square wave outputof rotor position sensor 11. For each of these timing pulses P, thedelay circuit 14 regulated by the power control potentiometer PCP beginsa delay period. There are three delay periods for each half cycle (180electrical) of the rotor position square wavebecause a timing pulse P isgenerated at each square wave edge of the threephase square wave. Thecontrol range of this delay period is from zero to one-third of a halfcycle, i.e., 60 electrical, and such delay period controls the openingof gates NAND47 NANDSZ (FIG. 6) in the delay gating circuit 22 so thatthe output of delay gating circuit 22 over lead C2 to interface circuitIFC2 is three square wave segments 02 per half cycle (See FIG. 3d) eachof which can be modulated from 0 to 60 of the half cycle. Assumingdelay, the resulting three current pulses CC2 from power Switch PSC2 perhalf cycle are shown in FIG. Se.

in a conventional synchronous motor the torque angle between the voltageapplied to the stator windings and the counter e,rn.f. generated by theflux of the resultant ampere turns varies from zero degrees at stall toalmost 90 at a higher motor speed. The phase relation (torque angle) ofthe conduction by the power switches PSA1-PSC2 with respect to thecounter e.m.f. generated in the stator power windings AlP-C2P (by theampere turns which produce the air-gap flux) determines whether themotor is operating as a generator or a motor and also determines at whatpower level the motor is operating,

At low motor speeds and small displacement (torque) angles betweencounter e,m.f. and power switch conduction, such as occur at a stallcondition, the stator winding looks like Substantially pure resistanceto the low frequency square waves produced by the power switches, whileat higher speeds the synchronous reactance increases and the statorwinding appears more like pure inductance to the battery. Consequently,it is desirable that the torque angle (i.e,, the phase angle between theinitiation of power switch conduction window and the counteremf.generated in the stator windings by the resultant ampere turns) be smallat low speeds so the stator field will be in step with the rotor andalso that the torque angle be leading at higher motor speeds (withconsequent higher synchronous reactance and lagging stator currents) sothat the rotor field stays in synchronism with the rotating statorfield.

The aforementioned US. Pat, No. 3,584,276 to W. L. Ringland et aldiscloses a variable speed synchronous motor drive system in which thedisplacement angle of the terminal voltage applied to the stator windingrelative to the magnetic poles generated in the rotor is continuouslyvaried as a function of motor speed to maintain the output power of themotor constant over the speed range.

in the preferred embodiment, the torque angle is limited to two discretevalues, namely 0 and 60. Such variation in phase angle at which powerswitch conduction is initiated can be either for forward or reverserotation of the motor and is in addition to the variable delay ininitiation of power switch conduction as a function of the setting ofpower potentiometer PCP provided by variable delay circuit 15. A torqueangle of 0 is used only at very low speeds and is necessary to maintainstall torque. A 60 leading torque angle is a slight compromise since itis used over a wide speed range in which torque angles of other than 60would yeild greater horsepower output from the motor, but it is adesirable compromise since the power output with 60 torque angle atmaximum motor speed is approximately 85 percent of that obtained withthe optimum 90 torque angle.

The speed direction circuit 16 provides signals to angle-directioncircuit 19 which determine the direction of rotation of the motor (asmanually selected by the direction switch DS) and also determine theproper torque angle of 0 or 60 as a function of motor speed. The phaseangle selection information is derived from the speed switch 17 whichdetermines whether the motor is turning faster or slower than apredetermined initial speed at which the motor power output for a torqueangle of 60 is equal to that for a 0 torque angle. This equalization isnecessary for a smooth transition upon changing the torque angle. Thepreferred v embodiment is for a wound rotor synchronous motor,

but the invention is also applicable to a variable speed brushlesssynchronous motor wherein magnetic poles are induced in a ferromagneticrotor carrying no windings by a field winding on the motor stator,

CAPACITIVE POSITION SENSOR The capacitive rotor position sensor 11 isdisclosed in the copending application of Frederick A. Stich, Ser.

No, 253,418, filed May 15, 1972. now US Pat. No. 3,760,382 entitlesCapacitive Position Sensor and hav. ing the same assignee as thisinvention, and establishes the correct sequence of enabling of the powerswitches PSAl-PSCZ with respect to the motor rotor. Another way ofstating this function is that capacitive rotor position sensor 11establishes the correct stator field sequence with respect to the rotorfield. Capacitive rotor position sensor 11, in combination with squarewave l' d rives a thrcc#ph se train of square waves A, A, B, B, C, and Cat a frequency proportional to rotor angular velocity shown inFiG. 3awhich is synchronized to the rotor position. If the output pulses fromcapacitive position sensor 11 were connected directly to the interfacecircuits lFAl-IFCZ to enable the power switches, the motor would rotatein the forward direction at full conduction and with the power switchconduction window in phase with the counter e.m.f. generated in thestator power windings AlP-C2P by the ampere turns which are theresultant of the rotor field ampere turns and the armature reactionampere turns.

Capacitive position sensor 11 may have 2pn equals twelve stationarymetallic capacitor plates, or electrodes 31 (See FIGS. 1, 2, 11 and 12)disposed side-byside and forming an annular disk (where n is the numberof phases and p is the number of rotor pole pairs) mounted on the motorstator. A rotatable capacitor plate shown in FIGS. 1 and 2 as comprisingtwo electrically commoned, elongated and narrow metallic electrodes 36aligned along a diameterof the circular disk 15 is operatively connectedto the motor rotor R for movement therewith and is mounted for rotationadjacent the stationary capacitor plates 31.

The rotatable position sensor electrodes 36 are schematically shown inFIG. 2 as electrically connected to each other and by a conductor 37 toa movable electrode 38 of a coupling capacitor C1 having a stationaryelectrode 39 coupled to the output of a position sensor relaxationoscillator 10 which is capable of producing fast time-rise pulses. Asdisclosed in the aforementioned US. Pat. No. 3,760,392 and shown inFIGS. 11 and 12, the stationary metallic position sensor electrodes 31may be copper plates in the shape of a sector of a ring affixed bysuitable means to a stationary annular stator board 40 mounted byfastening means 41 to the end bell 42 of the motor stator. Thestationary electrode of coupling capacitor C1 may be a thin annularcopper ring 39 affixed to stationary stator board 40 radially inwardfrom electrodes 31. The movable electrode of coupling capacitor C1 maybe a thin annular copper member 38 affixed to a rotating annular rotorboard 43 fastened to the motor rotor R. Movable electrode 38 of thecoupling capacitor C1 may have thin diametrically opposed fingers 36integral therewith extending radially outward which constitute therotatable plates 36 of the capacitive position sensor 11.

The high frequency pulses generated by relaxation oscillator 10 arecoupled through rotatable capacitor electrodes 36 to the adjacentstationary plates 31 and the load connected thereto. Oscillator 10provides read-out" pulses to the rotatable capacitor plates 36, andthese read-out pulses are distributed to the fixed capacitor plates 31.The highfrequency componentsof the read-out pulses readily couplethrough adjacent movable and fixed plates 36 and 31 into the loadconnected to the fixed plates 31. Inasmuch as the preferred embodimenthas a four-pole rotor, diametrically opposite plates 31 are displaced360 electrical degrees and are electrically connected together. Theoutputs from the fixed plates 31 of capacitive rotor position sensor 11are converted by square wave generator 12 into the SQUARE WAVE GENERATORSquare wave generator 12 inclues three identical differential amplifiers61A, 61B, and 61C (See FIG. 2) which are associatedwith the phases A, Band C respectively and produce the output for said phase.

Square wave generator 12 converts the read-out pulses received on therotor position sensor stationary plates 31a, 31b, 31c, 31d, 31e and 31)"into the set of threephase square waves A, B and C and their complementsA, E and C shown in, FIG. 3a having a frequency which is a functionofthe rotational velocity of the motor rotor. The motor rotor has fourpoles, and consequently each pair. of diametrically opposed positionsensor plates 31 (which are displaced 360 electrical degrees) areelectrically connected together. Each pair of diametrically opposed,electrically commoned position sensor stationary plates 31 is connectedto one of the inputs to each of the three differential amplifiers 61A,61B and 61C as shown in FIG. 2. Forexample, electrically commonedposition sensor stationaryplates 31a designated A, E, C are connectedthrough a resistor RA] to an A input of differential amplifier 61A,through a resistor RB2 to a E input of differential amplifier 61B, andthrough a resistor RC1 to a C input of differential amplifier 61C. Thedesignations A resistors, E resistors, C resistors, etc., connotes thatthe particular input resistor is connected to a pair of diametricallyopposed stationary electrodes 31 bearing this designation in FIG. 2 andwhich results in the corresponding output pulse being at logic 1 voltagewhen movable electrodes 36 are opposite these stationary plates.Resistors RAl are connected to the pairs of stationary electrodes 31a,31b and 31c each of which is designated A and which together subtend 180electrical and result in the generation of the A pulse during theinterval that rotating electrodes 36 have closer capacitive coupling tothese stationary capacitor plates than to the stationary electrodes 31d,31 e and 31f designated A. Similarly, RB2 input resistors are connectedto the pairs of stationary capacitor electrodes 31f, 31a and 31b all ofwhich are designated E and which together subtend 180 electrical degreesand result in the generation of the E square wave during the 180electrical interval when rotatable electrodes 36 are opposite thereto.The corresponding inputs to the phase differential amplifiers 61A, 61Band 61C are coupled to stationary plates displaced electrical degrees sothat the output pulses A, B and C have l20 electrical phasedisplacement, e.g., stationary plates 31a, 31b, 31c designated A coupledto load impedance LRA are displaced 60 (120 electrical) from plates 31c,31d and 31e designated B coupled to load impedance LRB.

Square wave generator 12 also includes three NAND gate latch circuitsLCA, LCB and LCC each of which is associated with one of the phases andthe differential amplifier for that phase. For example, differentialamplifier 61A and latch circuit LCA are associated with phase A andtogether generate the square wave pulse A for phase A shown in FIG. 3aand its negation A (which is the inverse of A).

The three differential amplifiers 61A, 61B and 61C are identical andonly the differential amplifier 61A for phase A will be described.Differential amplifier 61A is of conventional configuration, and thebase of one transistor Q23 is coupled to the three resistors RAl whichadd the signals from the pairs of position sensor stationary plates 31a,31b, and 31c respectively. The base of the other transistor Q24 ofdifferential amplifier 61A is coupled to the three A input resistors RA2which are individually connected to the pairs of position sensorstationary plates 31d, 312 and 31f and sum the signals therefrom.

Differential amplifier 61A provides a low voltage or logic output on thecollector of that transistor Q23 or Q24 having its base coupled to thethree pairs of position sensor stationary plates 31a, 31b, 310 or 31d,31e, 31f having the greatest coupling to the rotatable electrodes 36,thereby giving an indication of the position of the motor rotor R. Forexample, if rotatable plates 36 are in a position where the sum of thereadout pulses received on the pairs of plates 31a, 31b, and 31c,designated A, is greater than the sum of the pulses received on pairs ofstationary plates 31d, 31e, and 31f, designated A, transistor Q23 willbe turned on and the voltage on its collector will be low and transistorQ24 will be turned off and its c0llector potential will be relativelyhigh. 1

Differential amplifiers 61A, 61B, and 61C enhance the one-to-zero ratioof the inputs from capacitive position sensor 11 and control NAND gatelatch circuits LCA, [C R and LCC respectively which convert the enhanced pulses into the square waves A, A, B, B, C and C.

SYNCHRONOUS PULSE GENERATOR Synchronous pulse generator 14 receives thethreephase rotor position squa re waves A, E, and C and theircomplements A, E, and C from square wave generator 12 and generates atiming pulse P shown in FIG. 312 at every square wave edge of the outputfrom square wave generator 12. Synchronous pulse generator 14 thus formsa pulse train wherein each timing pulse P corresponds to a change ofstate in position sensor 11. Inasmuch as there are six edges per cycleof the three-phase square waves A, A, B, E, C and C, six timing pulses Pare derived by synchronous pulse generator 14 at a frequencyproportional to motor speed for each cycle of the three-phase squarewave output from square wave generator 12.

Synchronous pulse generator 14 shown in FIG. 2 includes a single-endeddifferential amplifier 70 of conventional design wherein the base of onetransistor 025 is coupled to the A, B and C leads from the latchcircuits LCA, LCB, and LCC of the square wave generator 12 throughindividual differentiating capacitors C3. The base of the othertransistor Q26 of differential amplifier 70 is coupled to the A, E, andC leads from square wave generator 12 through individual differentiatingcapacitors C4. The collectors of transistors Q25 and Q26 are commonedand connected to the output lead 75 in which the'train of synchronizingpulses P shown in FIG. 3b appears. The input capacitors C3 and C4differentiate the square wave output A, B, C, A, E and C from squarewave generator-l2, and the differential amplifier 70 is operated in an'overdriven mode and shapes the pulses to form a single train ofnegative going timing pulses P at the commoned collectors, as shown inFIG. 3b at a frequency indicative of motor speed and with a pulsegenerated at each change of state of the NAND gate latch circuits LCA,LCB, and LCC Of the square wave generator 12, i.e., at every square waveedge of the output pulses A, A, B, E, C and C from the position sensor11 and the square wave generator l2.

VARIABLE DELAY CIRCUIT If the three phase rotor position output A, B, C,A, E, C of square wave generator 12 directly controlled the powerswitches PSAl-PSCZ, the motor would rothe conduction window of the powerswitches in phase with the voltage generated by the rotor positionsensor 11. Control of motor speed and torque is accomplished by phasingback," or delaying the power switches from their full conduction; Statedin another way, speed and torque of the motor are selectively controlledby varying the duty cycle of the power switches PSAl-PSCZ, i.e., theportion of the conduction window during which the power switchesconduct. It will be appreciated that as the duty cycle of the powerswitches is increased, the average current carried by the statorwindings AlP, A2P, BlP, B2P, ClP and C2P, the torque on the rotor, andthe speed of the rotor R are correspondingly increased.

The initiation (and reinstatement) of conduction by power switchesPSA1-PSC2-is determined by pulses from drive oscillator 20. Timingpulses P (See FIG. 3b) from synchronous pulse generator 14 appearing inconductor are delayed in a variable delay circuit 15 through a phaseangle which is a function of the setting of power control potentiometerPCP to form the train 'of delay pulses P shown in FIG. 3c which triggerdrive oscillator 20 and enable gates NAND47 NANDSZ of the delay gatingcircuit 22 (See FIG. 6).

In the preferred embodiment the timing pulse P from synchronous pulsegenerator 14 shown in FIG. 3b are 60 apart, the variable delay circuit15 generates three delay pulses P per half cycle which are illustratedin FIG. 30 as having been delayed 30 relative to the timing pulses Pfrom synchronous pulse generator 14, and the power switch PSC2 conductsthree current pulses CC2 of 30 duration in each half cycle asillustrated in FIG. 3e. Inasmuch as there are three current pulses CC2per half cycle, if each delay pulse P is delayed by 0 to 60, the netduty cycle of the power switches PSA- l-PSCZ will vary from 0 to I".

Variable delay circuit 15 is shown in FIG. 4 and includes an input latchcircuit 76 comprising NAND gates NAND3 and NAND 4. Input latch circuit76 is set to form the trailing edge of a delay pulse P (shown in FIG.3c) each time a negative-going timing pulse P from synchronous pulsegenerator 14 on lead 75 is applied to the A input of gate NAND3. Inputlatch circuit 76 is reset" after a time delay to form the leading edgeof a positive going delay pulse P (shown in FIG. 3c) each time atransistor Q28 conducts and changes its collector voltage from high tolow to provide logic 0 on the B input to gate NAND4. The delay pulses Pgenerated at the output of gate NAND4 appear on output lead 78 which'isconnected to drive oscillator 20 and to delay gating circuit 22.

In the interim between timing pulses P from synchronous pulse generator14, circuit 76 is latched" with logic 1 on the A input and logic I onthe B input (pulse P) of gate NAND3 so that logic 0 appears on itsoutput at the leading edge of each delay pulse P. The logic 0 output ofgate NAND3 when input latch circuit 76 is reset is connected to the Ainput of a NAND gate NANDS which has logic I on its B input from a NANDgate NAND6, thereby providing logic 1 output from gate NANDS whichmaintains. two transistors Q30 and Q31 conducting and prevents charge ofa time delay capacitor C6. The series arrangement of thecollectoremitter circuit of conducting transistor Q31 and a diode D7 isin shunt to the series arrangement of timing capacitor C6 and a resistorR41 and maintains timing 15 capacitor C6 discharged when the input latchcircuit 76 is reset. in the reset condition of input latch circuit 76,the logic output from gate NAND3 is applied to the A input of gate NAND4to keep logic 1 on the output of gate NAND4 and on conductor 78 and thusmaintain delay pulse P' positive.

A negative-going timing pulse P from synchronous pulse generator 14 overlead 75 applies logic 0 to the A input of gate NAND3 to set latchcircuit 76 and thus provides logic 1 on the output of gate NAND3. Thelogic 1 output from gate NAND3 is coupled to the A input of gate NAND4and changes its output to logic 0 which forms the trailing edge of thepositive-going delay pulse P when input latch circuit 76 is set. Thelogic 0 output from gate NAND4 is coupled to the B input to gate NAND3to maintain the input circuit 76 latched in set condition with logic 1on the output from gate NAND3 even after input pulse P disappears. andlogic 1 again appears on lead 75 and the A input of gate NAND3.

The logic 1 on the output of gate NAND3 is applied to the A input to agate NANDS when input latch circuit 76 is set. The logic 1 from gateNAND3 and logic l from gate NAND6 applied to the A and B inputs of gateNANDS provides logic 0 output from gate NANDS which turns off transistorQ30. The turning of transistor 030 off lowers the forward bias on thebase of NPN transistor Q31 and turns it off. Turning transistor Q31 offpermits time delay capacitor C6 to begin to charge from the positiveterminal of the battery through a resistor R42 in series with theemittercollector circuit of a transistor Q34 which constitutes avariable current generator for the charging of time delay capacitor C6.The slider of power control potentiometer PCP is coupled over lead 74 tothe base of current generator transistor Q34, and the setting of powercontrol potentiometer PCP determines the forward bias on the base oftransistor Q34 and the charging current flowing to time delay capacitorC6, thereby determining the phase angle by which the delay pulses P fromvariable delay circuit are delayed relative to timing pulses P fromsynchronous pulse generator 14.

One electrode of time delay capacitor C6 is coupled through a diode D8to-the emittervof a transistor Q35 having its base coupled to thejunction of two resistors R43 and R44 which, in series with a resistorR45, form a voltage divider connected across the batteryterminals anddetermine the emitter potential at which transistor Q35 will begin toconduct. When the charge on time delay capacitor C6 reaches apredetermined potentiaL' transistor Q35 is turned on, and the change ofits collector potential is coupled to the base of transistor Q28 andturns it on. Conduction by transistor Q28 lowers its collector potentialfrom logic 1 voltage to logic 0 voltage which is coupled to the B inputto gate NAND4 to reset the input latch circuit '76 and provide logic Ion the output of gate NAND4. The logic 1 on the output of gate NAND4 andon conductor 78 is the leading edge of the delay pulse P from variabledelay circuit 15. The logic I from gate NAND4 is also coupled to the Binput to gate NAND3, thereby providing logic 0 output from gate NAND3 toreset the input latch circuit 76, and also provide logic 1 from gateNANDS to turn on transistors Q and Q3] and discharge time delaycapacitor C6.

Inasmuch as synchronous pulse generator 14 derives a timing pulse P ateach edge of the three-phase square wave output from square wavegenerator 12, three delay pulses P' will be'providedby the variabledelay cricuit 15 during each conduction window, and

ZERO DELAY SWITCH The minimum delay that can be provided by variabledelay circuit 15 is approximately 15 microseconds, but this is too longto permit the motor to deliver maximum output horsepower. A zero delayPNP transistor switch Q38 (F IG. 4) has its base coupled to the sliderof power control potentiometer PCP and its collector connected to thebase of NPN transistor Q28. When the slider of power controlpotentiometer PCP approaches its maximum setting, the base of zero delaytransistor switch Q38 becomes forward biased and it conducts. The changeof potential at the collector of transistors Q38 when it is turned on isapplied to the base of transistor Q28 and turns it on, thereby reducingthe collector potential of transistor Q28 and the B input of gate NAND4to logic 0 and maintaining logic 1 on the output lead 78 from variabledelay circuit 15 to assure that the delay pulses P to drive oscillator20 and delay gating circuit 22 are continous and that the power switchesPSAl-PSCZ conduct continously until the end of the 60 conduction period.

As discussed hereinbefore, the torque angle, or displacement angle,between the voltage applied to the stator winding and the countere'.m.f. generated by the air gap flux should ideally bevaried from zeroat stall to ninety degrees at a higher speed, but in the preferredembodiment the torque angle is limited to two discrete values, namely 0and 60 by varying the phase angle between the initiation of the powerswitch conduction window and the rotor position as a function of motorspeed. Stated another way, different angularly displaced rotor positionsignals selectively control the conduction windows of the power switchesin order to change torque angle as a function of motor speed. This is inaddition to the variation of the point of initiation of conductionwithin the conduction window for the purpose of regulating motor speedand torque.

The speed-directioncircuit 16 provides output signals on leads S 'F, 'F,S'F and S'E which determine the direction of rotation of the motor, asmanually selected by the direction switch DS, and also determine theproper torque angle of 0 or 60 as a function of motor speed. The torqueangle information is derived from )the speed switch 17 which determineswhether the motor is turning faster or slower than a predeterminedinitial speed at which the motor power output for a torque angle of 60is equal to that for a 0 torque angle.

SPEED SWITCH Speed switch 17 shown in FIG. 5 detects when motor speed isequal to the predetermined critical speed at which the torque angle ischanged between 0 and 60. The critical motor speed is set by arelaxation oscillator 83 which generates a train of pulses at areference frequency and includes a timing capacitor C9 which is chargedfrom the battery through a resistance R48 to a predetermined voltagewhich forward biases the emitter of a PNP transistor Q39 and turns it onto discharge the timing capacitor C9 and turn on a transistor Q40.

17 Conduction by transistor Q40 lowers its collector voltage andgenerates a negative-going, logic pulse which is coupled through a diodeD9 to the input of a NOT gate inverting amplifier NOT3 and also to the Binput of a NAND gate NAND4 of an input latch circuit 85.

The input to speed switch 17 is the train of negativegoing timing pulsesP over conductor 75 from the synchronous pulse generator 14 which areapplied to the A input of a NAND gate NAND6 of input latch circuit 85and also to the input of a NOT gate NOTS. The input latch circuit 85 isset by each logic 0 timing pulse P from the synchronous pulse generator14 to provide logic I from gate NAND6, and is reset by a pulse fromreference oscillator 83 to provide logic 0 from gate NAND6 and logic 1from gate NAND4.

The speed switch 17 also includes an output latch circuit 86 comprisingNAND gates NANDIO and NANDIl which is set (and also reset) by twosuccessive pulses from the same pulse train without an intervening pulsefrom the other pulse train. The output from gate NAND6 is coupledthroughan integrator circuit of resistor R49 and capacitor C10 to the B inputof a NAND gate NAND12 having its A input coupled to the output of gateNOTS and its output coupled to the A input of NAND gate NANDIO of theoutput latch circuit 86. A negative-going timing pulse P from thesynchronous pulse generator 14 will change the outputs of gates NOTS andNAND6 to logic I, and if the next pulse is also on lead 75 from thesynchronous pulse generator'l4, the output of gate NAND6 will still belogic 1 (since the input latch 85 has not been reset by a pulse from thereference oscillator 83 applied to gate NAND4), and gate NAND12 'willprovide logic 0 on its output to the A input of gate NANDlO, therebysetting the output of gate NANDlO and the output lead S to logic I,which indicates that the timing pulses P are coming in faster from thesynchronous pulse generator 14 than pulses from the reference oscillator83 and that the motor rotor is above the critical speed.

In a similar manner the output of gate NANDll on the 8 lead tospeed-direction circuit 16 is set to logic 1 when the pulses from thereference oscillator 83 occur faster than the timing pulses P from thesynchronous pulse generator 14.

The speed-direction circuit 16 receives logic I on the S lead from speedswitch'15 when the motor speed is above the critical speed and a 60torque angle is desired. Speed-direction circuit 16 receives logic I onthe F lead when the direction switch DS is operated to provide forwardmotor rotation and receives logic I on the 8 lead when direction switchDS is operated to reverse the direction of rotation of the motor.

DIRECTION SWITCH FIG. 1 schematically illustrates that a plus five volt(logic I source is connected through resistors R50 and R51 respectivelyto the F and F leads and that direction switch DS has normally closedcontacts 90 that clamp the P lead to ground when the switch is in theforward position and are opened to provide plus 5 volts (or logic I) onthe F lead when the switch DS is operated to the reverse position.Direction switch DS also has normally open contacts 91 which permit theF lead to be at logic 1 potential when the switch DS is in the forwardposition and are closed to clamp the F lead to ground (and logic 0) whenthe switch DS is operated to the reverse position. I

SPEED-DIRECTION CIRCUIT The speed-direction circuit 16 (See FIG. 6)includes a memory flip-flop latch 93 having a pair of three-input NANDgates NAND14 and NANDIS which lock the latch 93 in the conditionexisting when the signal on the S lead from the speed switch 15 goesfrom logic 0 to logic 1, i.e., when the motor exceeds the criticalspeed. Below the critical motor speed, logic 1 exists on the 8 lead andlogic 0 exists on the S lead and the memory latch 93 will respond to thesignals on the F and l leads from the direction switch DS to vary thelogic signals on the 8F, 8'8, SF and S? leads to angle-direction circuit19 and thus change torque angle and motor direction. Thus, if thedirection switch DS is reversed, the signals on leads F and F reverse tochange the direction of motor rotation, and the state of memory latch 93can change as long as the signal on lead 8 is l and the signal on lead Sis logic 0. As the motor speed rises above the critical value, thesignal on lead S becomes logic 1 and that on lead 8 becomes logic 0,locking the memory latch 93 and recording the status of direction switchDS at that time. As long as motor speed remains above the criticalspeed, a change in the direction switch D8 will not change the state ofthe memory latch 93 and thus will not change the direction of motorrotation.

The S lead from speed switch 17 is coupled to the C input of gate NAND14and also to the A input of gate NANDIS. The 8 lead is coupled to the Binput of a NAND gate NAND16 and the A input ofa NAND gate NANDI7. The Flead from direction switch DS is coupled to: (a) the A input of gateNAND16; (b) the B input of a NAND gate NANDZI; (c) to the A input ofgate NAND14; and (d) the B input to a NAND gate 23. The F lead fromdirection switch DS is coupled to: (a) the B input of gate NAND17; (b)the C input of gate NANDlS; (c) the A input of a NAND gate NAND20; and(d) the A input of a NAND gate NAND22. The output of gate NAND16 iscoupled to the A input of a NAND gate NAND18 having its output coupledto the B input of gate NAND14, and the output of gate NAND17 is coupledto the B input of a NAND gate NAND19 having its output coupled to the Binput of gate NANDIS of the memory latch 93.

Below Critical Speed Assume that logic 1 appears on the F and 8 leadsindicating respectively forward motor rotation and motor speed below thecritical speed, Under these conditions, the outputs of gates NAND14 andNANDlS will both be logic 1 because eachhas logic 0 on the S lead as aninput. The logic 1 outputs of gates NAND14 and NANDIS are coupled to theA and B inputs of a NAND gate NAND24 which provides logic 0 on itsoutput which is connected to the S lead. The logic 0 output of gateNAND24 is coupled to the input of a NOT gate NOT7 whose output-is logic1 and is connected to the 8 lead. The S' lead is coupled to the A and Binputs of gates NAND23 and NAND22 respectively, and the 8 lead iscoupled to the A and B inputs of NAND gates NAND21 and N ANDZOrespectively.

Still assuming logic I on the 8 and F leads, (which provide logic I onthe 8' lead as described above), the output of gate NAND20 will be logic0 since it has logic 1 on both its inputs. The logic 0 output of gateNANDZO is converted to logic 1 by a NOT gate NOTS to provide logic .I onthe S'F lead to the angle-direction output of the gates may berepresented:

GATE

NAND 14 NAND 1s NAND l6 NAND 17 NAND 1s NAND 19 NAND 20 NAND 21 NAND 22NAND 23 NAND 24 OUTPUT Logic on the output of gate NAND l8 and logic 1on the output of gate NAND 19 is the condition set in memory latch 93when the direction switch DS is in the forward position.

If direction switch DS is'now operated to the reverse.

position, logic 1 appears on the F lead and logic 0 on the'F lead.Theoutput of gate NAND16 changes to logic 0, the output of gate NAND17changes to logic 1, the output of gate NANDIS changes to logic 1, andthe output of gate NAN D '19 changes to 0. Gates NAND14 and NANDlS donot change states since each has a logic 0 input from the S lead. Theoutput of gate NANDZO becomes logic land the output of gate NANDZlchanges to logic 0 which is converted by gate NOT 9 to logic 1 on the8'? lead,

GATE

NAND 14 NAND 1 s NAND l6 NAND 17 NAND 1s NAND 19 NAND 2o NAND 21 NAND 22NAND 23 NAND 24 OUTPUT Above Critical Speed If the motor speed risesabove the critical speed when the direction switch DS is in the forwardposition, logic 1 appears on the S lead from speed switch and logic 0 onthe S lead. The logic 0 on the 3 lead changes the output of gate NAND17to logic 1, but gate NAND16 does not change its logic 1 output. Theoutput of gate NANDIS remains logic 0 and that of gate NAND19 logic 1,which is the condition set in memory latch 93 when direction swtich DSis forward. The logic 1 on the S lead changes the output of gate NANDISto logic 0 since it has logic 1 on all three inputs, but does not changethe logic 1 output of gate NAND14, thereby providing logic 1 output fromgate NAND24 or 1 the S lead and logic 0 output from gate NOT7 on the Slead. The output of gate NAND23 remains at logic 1, but the output ofgate NAND22 goes to logic 0 which is converted to logic I onthe outputof gate NOTlO and the S'F lead, thereby indicating that rotation of themotor above the critical speed in the forward direction with a torqueangle is desired. 7

The three-input NAN-D gates NAND14 and NANDIS compare the status ofmemory latch 93 with the status of direction lever DS when the motor isabove the critical speed. If the memory latch 93 and direction switch DSboth agree, either both forward or both reverse, then the 60 torqueangle is allowed, as indicated by S, equals logic 1. In the immediatelypreceding paragraph' the condition set in thememory latch 93 wasforward, i.e., logic 0 on gate NANDIS and logic 1 on gate NAND19, andagreed with the forward position of direction lever DS, therebyallowing. the 60 torque angle indicated by S equals logic 1.

If, however, the latch 93 and direction lever DS disagree, as wouldoccur if the vehicle were going forward above the critical speed andtheoperator changed the direction switch DS to call for reversal of themotor, then the torque angle is changed to 0 to provide braking actioneven though the speed switch 17 provides logic ion the .5 lead. This isnecessary because at high speeds motor operation with; a .l20torqueangle canbe similar to that at a 60,? torque angle, and changingthe direction switch DS from forward to reverse displaces the phaseangle by 180, thereby converting the 60 torque angle to Consequently, ifthe operator reversed the direction switch DS to reverse vehicledirection when the motor was above the critical speed, the vehicle wouldnot respond with braking and subsequent reversing action if S remainedlogic 1, but rather would continue to drive in the forward direction andmight even go faster. The speed-direction circuit 16 corrects this bychanging the torque angle from 60 to 0 when the direction switch DS isreversed and motor speed is above the critical speed.

Reversal of the direction switch DS under such high speed conditionsprovides logic 0 on the F lead and logic 1 on the I lead, the output ofgate NAND16 remains logic 1 and the output of gate NAND17 remains logic1 so memory latch 93 does not change states. The output of gate NAND14remains logic 1 since it has logic 0 on its B input from gate NAND18,but the output of gate NANDIS becomes logic 1 when lead F becomes logic0. The logic 1 output from both gates NAND14 and NANDIS provide logic 0output from gate NAND24 on the S lead and logic 1 on the output of gateNOT7 and the 8" lead. The logic 1 on the S and l leads provides logic 0output from gate NAND21 which is converted to logic 1 on the 8'? lead tocall 0 torque angle and for braking of the motor.

The logic 1 output of gate NANDlS when the motor is rotating forwardabove the critical speed and direction switch DS is reversed is thus abraking signal which provides logic 1 on the 8? lead (or on the 'F leadof the motor is rotating in the reverse direction) and results inbraking of the motor. In alternative embodiments different means such asa manually operated braking lever derive a braking signal, and thespeeddirection circuit is responsive to such braking signal to changetorque angle into a different quadrant to accomplish braking of themotor.

If the operator should change his mind and return direction switch DS tothe forward position, the memory latch 93 would not change states, butthe output of gate

1. An electronic commutation system for an electric motor having astator provided with n phase windings, where n is an integer greaterthan one, a rotor rotatable within said stator, and means for generatingmagnetic poles in said rotor comprising, in combination, an electricalpower source, at least n controllable semiconductors arranged to conductcurrent from said power source to said stator phase windings in apredetermined sequence, rotor position sensor means for derivingtime-displaced square wave rotor position signals at a frequencyproportional to rotor angular velocity indicative of the position ofsaid rotor within said stator, commutation switching means including nlogic gate sets each of which sets is associated with one of said statorwindings and includes a plurality of logic gates receiving rotorposition signals and control signals as inputs for sequentially enablingsaid semiconductors so that said stator windings Generate a rotatingmagnetic field in synchronism with said rotor poles, said logic gatesbeing enabled when the control signal and rotor position signal inputsthereto occur simultaneously, the logic gates of each set receivingrotor position input signals displaced by predetermined angles,corresponding logic gates of said n sets receiving time-displaced rotorposition signals that occur in a sequence which results in said statorwindings generating a rotating magnetic field, means associated witheach logic gate set and responsive to the enabling of any logic gatethereof for deriving an enabling signal for the associatedsemiconductor, and means for selectively coupling control signalssimultaneously to the corresponding gates of said n sets, whereby thetorque angle of said motor may be selectively varied.
 2. In thecombination of claim 1 and including means for selectively varying thepower duty cycle of said semiconductors during said semiconductorenabling signals.
 3. In the combination of claim 2 wherein said meansfor generating magnetic poles in said rotor includes a field winding,means for energizing said field winding, and adjustable means forselectively varying the energization of said field winding.
 4. In thecombination of claim 3 wherein said means for selectively varying powerduty cycle includes an adjustable element, and said means for varyingfield winding energization is responsive to regulation of saidadjustable element so that said adjustable element simultaneouslycontrols both field winding current and power duty cycle.
 5. In thecombination of claim 2 wherein said power duty cycle varying meansincludes n delay gating means each of which has its input coupled to theassociated means for deriving a semiconductor enabling signal and itsoutput coupled to one of said semiconductors, and means for selectivelyadjusting the time interval that said n delay gating means are openedduring said rotor position signals.
 6. In the combination of claim 5wherein said means for selectively adjusting the time interval that saiddelay gating means are open includes means for deriving a plurality oftiming pulses during each of said rotor position signals, means forgenerating a delay pulse from each of said timing pulses after apredetermined time delay and being selectively adjustable to vary saidtime delay, and means for opening said n delay gating means during eachof said delay pulses.
 7. In the combination of claim 2 wherein saidrotor position signal deriving means generates signals of 180 electricaldegree duration and said power duty cycle varying means includes gatingmeans between each logic gate set and the associated semiconductor forturning said semiconductor on a plurality of times during the 180electrical degree duration of the semiconductor enabling signals, andmeans for selectively varying the time said semiconductors carry currenteach time they are turned on.
 8. In the combination of claim 7 whereinsaid rotor position signal deriving means generates n rotor positionsignals and their complements, said gating means includes synchronouspulse deriving means for generating a timing pulse at the leading edgeof each rotor position signal, and said means for selectively varyingthe time said semiconductors carry current includes means for turning ona semiconductor after a time delay each time a timing pulse occursduring the semiconductor enabling signal and variable time delay meansfor selectively varying the time delay interval between the occurrenceof a timing pulse and initiation of current conduction by saidsemiconductor.
 9. In the combination of claim 2 wherein said power dutycycle varying means includes means for turning each of saidsemiconductors on a plurality of times within the duration of thesemiconductor enabling signal, and means for selectively varying thetime said semiconductors carry current each time they are turned on. 10.In the combination oF claim 2 and including 2n controllablesemiconductors, and wherein said motor stator has n center-tapped phasewindings with the halves of each phase winding connected in series withsaid source and one of said semiconductors so that the magnetic fluxesgenerated by said winding halves are in opposite directions.
 11. In thecombination of claim 10 wherein said rotor position signal derivingmeans generates n rotor position signals of 180 electrical degreeduration displaced 360/n electrical degrees apart and also generatestheir complements, and wherein said semiconductor enabling signalgenerating means includes means for deriving signals which arecomplements of each other for enabling the semiconductors associatedwith the halves of each stator phase winding so that the winding halvesoperate in push-pull.
 12. In the combination of claim 1 wherein each ofsaid logic gate sets includes first and third logic gates, said firstgates of said n sets receive first rotor position signals displaced360/n electrical degrees apart and said third gates of said n setsreceive third rotor position signals displaced 360/n electrical degreesapart that are also displaced by a predetermined phase angle from aidfirst rotor position signals to thereby permit selective variation ofthe torque angle of said motor.
 13. In the combination of claim 12 andincluding means for deriving a speed signal when said motor attains apredetermined speed, and wherein said first and third gates of said nsets receive first and third rotor position signals displaced by such apredetermined phase angle that the motor output torque at saidpredetermined speed when said first gates are enabled is approximatelyequal to that when said third gates are enabled, and wherein said meansfor selectively coupling is responsive to said speed signal for removingcontrol signals from said first gates and for coupling control signalssimultaneously to said third gates.
 14. In the combination of claim 13wherein said first and third rotor position signals are displaced byapproximately 60 electrical degrees and effect motor torque angles ofapproximately 0* and approximately 60*, respectively.
 15. In thecombination of claim 1 wherein the corresponding logic gates of said nsets receive rotor position signal inputs displaced 360/n electricaldegrees apart.
 16. In the combination of claim 1 wherein each of saidlogic gates sets includes first and second logic gates, said first gatesof said n sets receive time-displaced first rotor position signals andsaid second gates of said n sets receive time-displaced second rotorposition signals inputs displaced by a predetermined phase angle fromsaid first rotor position signals, and said means for selectivelycoupling includes means for selectively coupling control signalssimultaneously to said first gates of said n logic gate sets and to saidsecond gates of said n logic gate sets.
 17. In the combination of claim16 wherein said second time-displaced rotor position signals aredisplaced 180 electrical degrees from said first rotor position signalsto thereby permit selective reversal of the direction of rotation ofsaid rotor within said stator.
 18. In the combination of claim 17 andincluding motor direction selecting means for selectively derivingforward and reverse signals, and wherein said means for selectivelycoupling includes means responsive to said forward and reverse signalsfor respectively coupling control signals simultaneously to said firstgates of said n logic gate sets and to said second gates of said n logicgate sets.
 19. In the combination of claim 18 wherein each of said logicgate sets includes a third gate, said third gates of said n sets receivetime-displaced third rotor position signal inputs displaced by apredetermined phase angle from said first rotor position signals, andincluding means for deriving a speeD signal when said motor rotorattains a predetermined angular velocity, and wherein said means forselectively coupling includes means responsive to generation of saidspeed signal when said forward signal is present for coupling controlsignals simultaneously to said third gates of said n sets of logicgates.
 20. In the combination of claim 19 wherein each of said logicgate sets includes a fourth gate, said fourth gates of said n logic gatesets receive fourth rotor position signal inputs displaced by apredetermined phase angle from said second rotor position signal, andwherein said means for selectively coupling includes gate meansresponsive to derivation of said speed signal when said reverse signalis present for coupling control signals simultaneously to said fourthgates of said n sets of logic gates.
 21. In the combination of claim 20wherein said means for selectively coupling includes means responsive toreversal of said motor direction selecting means when both said forwardand speed signals are present for removing control signals from saidthird gates and coupling control signals simultaneously to said secondgates of said n logic gate sets to thereby brake said motor and alsobeing responsive to reversal of said motor direction selecting meanswhen both said speed and reverse signals are present for removingcontrol signals from said fourth gates and coupling control signalssimultaneously to said first gates of said n sets to thereby brake saidmotor.
 22. In the combination of claim 19 and including means forderiving a brake signal, and wherein said means for selectively couplingincludes means responsive to derivation of said brake signal when saidspeed signal is present to remove control signals from said third gatesof said n sets and to couple control signals simultaneously to saidsecond gates of said n sets of logic gates to thereby brake said motor.23. In the combination of claim 19 wherein said means for generatingmagnetic poles in said rotor includes a field winding and field currentregulating means responsive to said speed signal to supply current ofpredetermined magnitude to said field winding, whereby regenerativebraking of said motor is possible.
 24. In the combination of claim 15having means including an adjustable element for selectively varying thepower duty cycle of said semiconductors when they are enabled, andwherein said field current regulating means in the absence of said speedsignal varies field current to said field winding as a function of thesetting of said adjustable element so that said adjustable elementsimultaneously controls both field winding current and power duty cycle.25. In the combination of claim 18 wherein said n logic gate sets alsoinclude third logic gates which receive third time-displaced rotorposition signal inputs which are also displaced by a predetermined phaseangle from said first rotor position signals to thereby permit variationof the torque angle of said motor when it is rotating in the forwarddirection and fourth logic gates which receive fourth time-diplacedrotor position signal inputs which are also displaced by a predeterminedphase angle from said second rotor position signals to thereby permitvariation of the torque angle of said motor when it is rotating in thereverse direction.
 26. In the combination of claim 25 and includingmeans for deriving a speed signal when said motor attains apredetermined speed, and wherein said means for selectively couplingincludes gate means responsive to derivation of said speed signal whensaid forward and reverse signals respectively are present for couplingcontrol signals simultaneously to said third gates and to said fourthgates.
 27. In the combination of claim 26 and including means forselectively delaying initiation of conduction by said semiconductorswithin the period of said rotor position signals during which they areenabled.
 28. In the combination of claim 26 wherein said means forgeneratinG magnetic poles in said rotor includes a field winding andfield current regulating means for energizing said field winding andbeing responsive to said speed signal to supply a current ofpredetermined magnitude to said field winding, whereby said motor can beregeneratively braked when it is operating above said critical speed.29. In the combination of claim 16 and including means for deriving abrake signal, and wherein said means for selectively coupling isresponsive to said brake signal to remove control signals from saidfirst gates and to couple control signals simultaneously to said secondgates and said second rotor position signals are displaced by apredetermined phase angle from said first rotor position signals whicheffect a motor torque angle that reduces motor torque in comparison tothat effected by said first rotor position signals.
 30. In thecombination of claim 1 wherein said n logic gate sets have first gateswhich receive first rotor position signals displaced 360/n electricaldegrees apart, third logic gates which receive third rotor positionsignals displaced 360/n electrical degrees apart and also displaced by apredetermined phase angle from said first signals to thereby permitvariation of the torque angle of said motor, and second logic gateswhich receive second rotor position signals displaced 360/n electricaldegrees apart and also displaced 180 electrical egrees from said firstsignals to thereby permit reversal of the direction of rotation of saidrotor within said stator.
 31. In the combination of claim 30 andincluding means for deriving a speed signal when said rotor attains apredetermined angular velocity, and wherein said means for selectivelycoupling includes gate means responsive to said speed signal forcoupling control signals simultaneously to said third gates of said nsets of logic gates.
 32. In the combination of claim 31 and includingmotor direction selecting means for selectively deriving forward andreverse signals, and wherein said means for selectively couplingincludes gate means responsive to said forward and reverse signalsrespectively in the absence of said speed signal to couple controlsignals simultaneously to said first gates of said n sets and to saidsecond gates of said n sets.
 33. In the combination of claim 32 whereinsaid n sets of logic gates also include fourth gates which receivefourth rotor position signal inputs displaced 360/n electrical degreesapart and also displaced by a preselected phase angle from said secondrotor position signals such that the motor output torque at saidpredetermined angular velocity is approximately the same when saidsecond gates are enabled and when said fourth gates are enabled, andsaid means for selectively coupling includes means responsive to thegeneration of said speed signal when said reverse signal is present forremoving control signals from said second gates and simultaneouslycoupling control signals to said fourth gates of said n sets.
 34. In thecombination of claim 33 wherein said means for selectively couplingincludes logic gate memory latch means receiving said forward, reverseand speed signals as inputs for permitting operation thereof in responseto said forward and reverse signals in the absence of said speed signaland for, when said speed signal is present, removing control signalsfrom said third gates and coupling control signals simultaneously tosaid second gates in response to operation of said direction selectionmeans in a direction to derive said reverse signal to therebyregeneratively brake said motor.
 35. An electronic commutation systemfor an electric motor having a pluraity of stator windings and a rotorrotatable in response to energization of said stator windings,comprising a source of electrical power, a plurality of controllablesemiconductors between said source of power and said stator windingsoperative to periodically Connect and disconnect said stator windings ina predetermined sequence to said source of power so that said statorwindings generate a rotating magnetic field, rotor position sensor meansfor deriving time-displaced, square wave rotor position signals at afrequency proportional to rotor angular velocity indicative of theinstantaneous relative positions of said rotor and said stator windings,electronic commutation means including a plurality of logic gatesassociated with each of said stator windings receiving rotor positionsignals as inputs for sequentially enabling said semiconductors so thatsaid stator windings generate a rotating magnetic field, the first gatesof said plurality of gates receiving time-displaced first rotor positionsignals as inputs and the third gates thereof receiving time-displacedthird rotor position signals as inputs that are also displaced by apredetermined angle from said first rotor position signals, said logicgates also receiving control signal inputs and being enabled when therotor position and control signal inputs thereto occur simultaneously,and means for selectively coupling control signals simultaneously tocorresponding logic gates, whereby the torque angle of said motor may beselectively varied.
 36. An electronic commutation system in accordancewith claim 35 wherein said motor has n stator windings, where n is aninteger greater than one, said first rotor position signals aredisplaced 360/n electrical degrees apart and said third rotor positionsignals are displaced 360/n electrical degrees apart.
 37. An electoniccommutation system in accordance with claim 36 wherein the power outputof said motor at a predetermined speed is approximately the same at apredetermined relatively low and at a predetermined relatively highmotor torque angle, and wherein said first and third rotor positionsignals are displaced by the angle between said relatively high andrelatively low motor torque angles.
 38. An electronic commutation systemin accordance with claim 37 and including means for generating a speedsignal when said motor attains said predetermined speed, said means forselectively coupling is responsive to the absence of said speed signalto couple control signals simultaneously to said first gates and isresponsive to said speed signal to couple control signals simultaneouslyto said third gates.
 39. An electronic commutation system in accordancewith claim 38 wherein the second logic gates of said plurality of gatesreceive time-displaced second rotor position signals displaced 180electrical degrees from said first rotor position signals, whereby thedirection of rotation of said motor may be selectively reversed.
 40. Anelectronic commutation system for an electric motor in accordance withclaim 38 and including motor direction selecting means for selectivelyderiving forward and reverse signals, and said means for selectivelycoupling includes means responsive to said forward and reverse signalsin the absence of said speed signal or respectively coupling controlsignals simultaneously to said first gates and to said second gates. 41.An electronic commutation system for an electric motor in accordancewith claim 40 wherein the fourth gates of said plurality of gatesreceive fourth rotor position signal inputs displaced by a predeterminedphase angle from the second rotor position signals, and wherein saidmeans for selectively coupling includes latch means responsive toderivation of said speed signal when said reverse signal is present forcoupling control signals simultaneously to said fourth gates.
 42. Anelectronic commutation system for an electric motor in accordance withclaim 41 wherein said latch means includes means for deriving a brakesignal when said speed signal is present and said motor directionselecting means is actuated in a direction to derive said reversesignal, and said means for selectively coupling is responsive to saidbrake signal to reMove control signals from said third gates and tocouple control signals simultaneously to said second gates to therebybrake said motor.
 43. An electronic commutation system for an electricmotor in accordance with claim 42 wherein said latch means also includesmeans responsive to said speed signal and actuation of said motordirection means in a direction to derive said forward signal forderiving said brake signal, and said means for selectively coupling isresponsive to said brake signal to remove control signals from saidfourth gates and couple control signals simultaneously to said firstgates to thereby brake said motor.
 44. An electronic commutation systemfor an electric motor in accordance with claim 35 wherein the motoroutput torque when said second gates are enabled is less than when thirdgates are enabled, and including means for deriving a brake signal, andwherein said means for selectively coupling includes means responsive tosake brake signal to remove control signals from said third gates and tocouple control signals simultaneously to said second gates to therebyregeneratively brake said motor.
 45. An electronic commutation system inaccordance with claim 35 and including means for selectively varying thepower duty cycle of said semiconductors during said rotor positionsignals.
 46. An electronic commutation system in accordance with claim45 wherein said rotor position sensor means generates square wave rotorposition signals of 180 electrical degrees duration, said power dutycycle varying means includes means for turning said semiconductors on aplurality of time during the 180 electrical degree duration of saidrotor position signals, and means for selectively varying the time saidsemiconductors carry current when they are turned on.
 47. An electroniccommutation system in accordance with claim 46 wherein said motor has atleast n stator phase windings, where n is an integer greater than one,said rotor position sensor means generates n rotor position signals andtheir complements, said means for turning said semiconductors on aplurality of times includes synchronous pulse deriving means forgenerating a timing pulse at the leading edge of each rotor positionsignal, and said means for selectively varying the time saidsemiconductors carry current includes means for turning on asemiconductor after a time delay each time a timing pulse occurs andvariable time delay means for selectively varying the time delayinterval between the occurence of a timing pulse and initiation ofcurrent conduction by said semiconductor.
 48. An electronic commutationsystem for an electric motor in accordance with claim 39 wherein saidpower duty cycle varying means includes a delay gating means associatedwith each said stator winding having its input coupled to the output ofsaid plurality of gates and its output coupled to the associatedsemiconductor, and means for selectively adjusting the phase angle atwhich said delay gating means are opened during said rotor positionsignals.
 49. An electronic commutation system for an electric motor inaccordance with claim 48 wherein said means for adjusting the phaseangle at which said delay gating means are opened includes means forgenerating a plurality of timing pulses during each of said rotorposition signals, means for generating a delay pulse from each of saidtiming pulses after a predetermined time delay, means for selectivelyvarying said time delay between said timing and delay pulses, and meansfor opening said delay gating means during each of said delay pulses.50. An electronic commutation system for an electric motor in accordancewith claim 49 wherein said motor has at least n sator windings, where nis an integer greater than one, and said rotor position signal derivingmeans generates n rotor position signals of approximately 180 electricaldegrees duration displaced 360/n electrical degrees apart and theircomplements and said timing pulse generating means derives a timingpulse at the leading edge of each of said rotor position signals.
 51. Inthe combination of claim 35 wherein said means for sequentially enablingsaid semiconductors includes NAND gate means associated with each statorwinding receiving the outputs of the associated plurality of logic gatesfor deriving an enabling signal for the associated semiconductor.
 52. Anelectronic commutation system for an electric motor in accordance withclaim 51 wherein each stator winding has a center tap, and twocontrollable semiconductors are associated with each stator winding eachof which is connected in series with said source and one of said statorwinding halves so that the magnetic fluxes generated by the windinghalves of each stator winding are in opposite directions, saidsemiconductor enabling signal being coupled to one of the semiconductorsassociated with each stator winding through a NOT gate so that it isenabled by the inverse of the signal which enables the othersemiconductor associated with said stator winding, whereby said statorwinding halves operate in push-pull.